1. Field of the Invention
The present invention relates to CMOS (complementary metal-oxide semiconductor) Integrated circuits (IC's) and more specifically to a charge pump level converter (CPLC) for translating low core 1-V to high-speed 3.3-V I/O interface.
2. Description of Related Art
Advances in CMOS technology are driving the operating core voltage of IC's lower. As device dimensions shrink, the voltage of the core logic, scales down proportionally in order to avoid gate-oxide breakdown and hot electron effects.
However, the 3.3-V I/O interface remains constant.
Complex integrated circuits operating with supply voltages of 1-V or lower have been demonstrated. In order to incorporate these circuits into existing systems it is necessary to provide interfaces from the low voltage logic to logic devices operating at 3.3-V or higher.
The often seen level converter is DCVS (Differential Cascode Voltage Switch) shown in FIG. 1. The DCVS shown in FIG. 1 becomes too slow or fails, and is unacceptable because the core voltage approaches or is even lower than the threshold voltage Vt of the thick oxide device of the 3.3-V MOSFET.
The low voltage NMOS's (MN11, MN21) are exposed to the I/O high drain voltage that can give electrons sufficient energy that they are injected into the gate oxide and cause permanent damage also known as hot electron effect.
In order to protect the 1.0-V NMOS transistors (MN12, MN22) from high drain voltage stress, a zero-Vt 3.3-V NMOS (MN11, MN21) transistors are used to isolate the output node voltages OUT and {overscore (OUT)} from transistors MP11 and MP21 as shown in FIG. 2.
This approach is utilizing a large layout area, it is too slow due to the large zero-Vt NMOS device which has large parasitic capacitive loading on the output node, and the fabrication process must provide for native device which is not readily available in conventional CMOS fabrication process.
Related art on the subject of level-up converters circuits has been presented in the literature by:    [1] Y. Kanno, et al, “Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIs,” in Proc. of Symp. On VLSI Circuit, June 2000, pp. 202-203.    [2] Wen-Tai Wang,: Level shifters for high-speed 1-V to 3.3-V interfaces in a 0.13 um Cu-interconnection/low-k CMOS technology,” in VLSI Technology, Systems and Applications, 2001. Proc. Of Technical Papers, 2001 International Symposium, 2001 pp 301-307.,    [3] Kan M. Chu and David I. Pulfrey, “Design Procedures for Differential Cascode Voltage Switch Circuits”, IEEE journal of Solid State Circuits Vol SC-21, No 6, pp 1082-1087 pp. 1-82-1087, Dec 1986.    [4] U.S. Pat. No. 6,356,137 Voltage boost circuit with low power supply voltage by Farzan Roohpavar    [5] K. Joe Hass, David F. Cox: Level Shifting Interfaces for Low Voltage Logic, 9th NASA Symposium on VLSI Design 2000    [6] Seong-Oak Jung, Ki-Wook Kim Sung-Mo Kang: “Low-Swing Clock Domino Logic Incorporating Dual Supply and Dual Threshold Voltages”
However none of the above related art achieve high speed from 1-V to 3.3-V I/O interface, use only basic CMOS devices and result in smaller layout area.